ASIC DFT Engineer

Chipright seeks highly motivated and experienced Design For Test (DFT) engineer to work closely with our customer. We require an engineer to work with leading-edge EDA tools in delivering an RTL design to GDSII. This is a fantastic opportunity for talented engineers to work within a team of highly experienced engineers.

Requirements 
7+ years experience in development of ASIC designs 
Proficient with VHDL & Verilog 
Proficient with Synopsys DC Shell & Primetime
Ability to influence the architecture-level and RTL-level design to ensure performance and area targets can be achieved 
Experience with scan synthesis and ATPG
Experience with Scan Insertion Logic, Scan cells, Memory BIST, JTAG, Boundary Scan, Design Sign off, Constraints 
Experience with UPF
Experience with scripted flows – Tcl, Perl
Experience in developing multiple process/library options 
Experience in working with EDA tool suppliers to yield the best results from their tools 
Strong debug & problem-solving skills 
Educated to degree level with excellent analytical, communication and documentation skills
Flexibility to travel
 Desirable  
Spyglass – Linting and Power aware Verification – MVRC Checks