Analog Designers with Verification Experience 
Master’s degree in Electrical Engineering or similar.
Minimum 7+ years experience working in analog mixed-signal verification.
Ability to create and verify Verilog-A and Verilog-D models..
Must be able to run analog simulations and extracted simulations.
Prior experience working on CMOS image sensor chips.
Previous experience and knowledge of chip top-level integration and verification, ideally with experience using SystemVerilog and python.
Candidate must be able to create and run digital test cases.
Proven record and experience enabling chip design blocks in tape-outs.
Excellent written and oral communication skills.