Area of expertise: ASIC Digital Layout & Physical Design
Core Technologies: Artificial Intelligence (AI)
Experience: 12 years
Time On Site: 10%
Top and block level digital implementation and signoff activities. Planning and managing physical design tasks for a successful chip implementation. Requirements gathering and customer interaction. Flow development in Cadence EDA (Innovus, QRC, Tempus, Voltus, Conformal) and Calibre DRC/ERC/LVS/ANT. RnD team guidance for timing constraints and synthesis activities.