Verification language: SystemVerilog (UVM) - several years? experience 
Python, C, C++
Simulators: Cadence Xcelium/IES/NCSim, Synopsys VCS, Mentor ModelSim
Protocols: AXI, DisplayPort, MIPI SCI2

Projects:
-       Verification of MIPI CSI2 Transmitter 
-       DisplayPort VIP (DisplayPort version 1.3)
-	DDR Cache Controller	
-	W2N (wide-to-narrow) adapter	
-	NVMe Inbound Controller
-       IP for Hardware Acceleration of Write Commands
-       IP for Buffer Management between System side (internal protocol) and Host side (NVMe)