Hardworking, enthusiastic and highly committed to the growth and success of the project. Interested in new technologies and solving complex technical issues. 

Technologies: VLSI (FrontEnd), FPGA, RTL, UVM, DSP, SDR
Languages: Verilog, VHDL, SystemVerilog, Python, TCL, ASM, C, C++, Golang
VLSI (FrontEnd) design: 
- RTL design, Verification, Synthesis
- IDE: Cadence/Synopsys toolset for RTL-design, Linting, Verification, Coverage analysis, Synthesis/STA