A motivated and dedicated digital IC design engineer with experience in digital frontend design flow, from initial conception through design and verification. 

Advanced VHDL, Verilog, SystemVerilog, UVM, GIT
Intermediate UNIX, Shell Script, C/C++, MATLAB, Python
Experience with Cadence tools (simulations), Synopsys tools (synthesis, logic equivalence check, STA, ATPG) and RealIntent tools (CDC, Reset domain crossing, Lint)
Worked closely with digital leader on architecture definitions
Creating verification test plans based on specs
Functional coverage, assertion coverage, code coverage
Experience with SPI, I2C, UART and AHB interface
Experience with integration and verification of ARM Cortex-M0/M4 processor
Experience with low power design techniques and UPF simulations
Preparation of design for production testing: scan-chain and BIST