Senior Analog IC Layout Engineer
 	
-Experienced in technologies from 180nm down to 55nm and 40nm
 	
-Deep understanding of semiconductor manufacturing process, device matching, isolation, power planning, ESD protection strategies and noise reduction
 	
-Have implemented wide range of analog layouts from custom blocks up to full-chip top-levels
 	
-Familiar with Cadence tools, linux environment, different verification tools (Calibre, PVS, Assura) and Microsoft Office
 	
-Worked on different analog and digital blocks (Bias, ADC, DACs, Regulators, Comparators, LDO, Oscillator)
 	
-DRC/LVS/ Antenna checks /Parasitic Extractions