Digital Verification Engineer

Universal Verification Methodology (UVM)
SystemVerilog 
VHDL
Assertion Based Verification
Functional Verification 
Python

Top and block-level verification:
- Building UVM test benches from scratch
- Writing reference golden models
- Writing constrained random and direct tests
- Integration of golden C models via DPI-based wrappers
- RTL and golden C models debugging
- Participated in development and implementation of department methodology processes
- Writing verification/coverage plans and other kinds of documentation
- Worked with AMBA protocols (APB/AHB)
- Writing assertions for functional and protocol checks