Considerable experience in Analog Layout 
Custom Analog IC  layout design and verification Cadence Virtuoso up to IC6.1.7, 
Assura, Calibre
Module and chip level IC layout, process nodes: 28nm to 2um
Experience working on band-gap references, Oscillators, EEPROM, OP-AMP, ADC, SRAM, ROM, RF detector, Comparators, LDOs, pseudo resistors working on the top level.
Digital Layouts: Standard cells, Pad cells, place and route of multiple digital blocks including one for single and multiple channels touch sensors.