AMS design and verification Engineer

Modeling:
- Design of WREAL/VAMS models according to schematics and 
specifications
- Matching model vs schematics
- Integration in top level

Top level mixed-signal verification: 
- Writing tests regarding test cases specification
- Running and debugging simulation

Digital verification:
- Running and debugging regression
- IP coverage closure (writing tests, basic UVC component dev elopment)

- Digital verification:
- SystemVerilog verification environment implementation according to 
UVM methodology 
- Writing testbench and test configuration
- Verification plan and table of checkers

Modeling:
- Design and simulation of simple models (VAMS, WREAL and VHDL)