-Experience in layout design of custom mixed-signal integrated circuits with great team-work skills and able to work with cross-functional teams
-Experience in leading projects and chip level layout design with FinFET & MOSFET processes
-Strong familiarity with Cadence Virtuoso Layout (XL, GXL), Assura, Calibre, ICV for the verifications like ``LVS, DRC, ERC, PEX'', RC extraction & EM/IR analysis tool Silicon Frontline
R3D, Cadence EAD and Unix
-Strong knowledge about layout techniques such as matching, shielding, isolating, minimizing parasitics & resistance, deep N-well structure, considering low noise - low power consumption, constraint- based layout, DFM best practices
-Strong understanding of guard rings and advanced process effects such as WPE, Latch-up, STI/LOD, Antenna effect, Electromigration, Mechanical stress