Area of expertise: ASIC Verification
Core Technologies: Automotive
Experience: 8 years
Time On Site: 5%
Universal Verification Methodology (UVM) 
SystemVerilog: - Top and block-level or from scratch 
- Golden models - Constrained random and direct 
tests - Golden models in C and DPI-based wrappers - 
RTL and golden models debugging - Verification and 
coverage plans documentation - AMBA protocols - 
Assertions for functional and protocol checks - 
Assertion Based Verification - UVM RAL