Area of expertise: ASIC Design
Core Technologies: Other
Experience: 12 years
Time On Site: 0%
Worked on UWB(Ultra Wideband) projects. Extended the Verification environment with new components and
checks based on the plan. Created tests and covergroups. Ran regressions and performed debugging.
Analyzed the IEEE standard and extracted digital design requirements for the Transmission part.
Was involved in Transmitter Digital Architecture.
Created testbench components from scratch and integrated them to the main verification environment.
Created Random driven test cases, trying to hit corner cases where design could be unstable.
Collected and analyzed code and functional coverage results.
Ran regressions and analyzed results, improving coverage and debugging design.
Worked closely with the Design and System team debugging and clarifying the Design and System
Languages: Verilog, System Verilog, Perl 
Technologies: OVM, UVM 
Tools: VCS, IRUN, XCELIUM, SimVision, Verdi, IMC, DVE 
Other: Jira, SVN