V-Plan & Verification Specification Development 
UVM TB Design, UVM Hierarchy & Test cases 
IP Verification, SVA, FC, FPV, Metrics Driven 
Digital (RTL) Design Specification Development 
RTL Implementation, SystemVerilog & VHDL 
IP Design, Integration & Documentation 
DSP Functions Implementation & Validation 
DSP Processor & CPU Development 
Ethernet, ARM (AXI, APB), MATLAB

Design Tools: Polarion, QuestaSim, QuestaFormal, Xcelium, JasperGold, Cadence V-Manager, Synopsys SpyGlass, Hansoft, Jira, Git.