Area of expertise: ASIC Digital Layout & Physical Design
Core Technologies: IoT (Internet of Things)
Experience: 18 years
Time On Site: 100%
Professional experience on ASIC/VLSI design, focused at Physical digital SoC (Systems-on-Chip) for communications and embedded computing systems. Experience on the whole ASIC/IC design flow, including IPs (Intellectual Property)(micro/nano-electronics); IP/SoC design for PCI-Express interfaces; CPqD ICT, Optical Technologies/Convergent Networks (GTO/DRC), as a Sr. R&D ASIC Design Engineer, acting on High-Level Synthesis, Physical Synthesis and Virtual Prototyping for high-speed optical communication networks and DSP algorithms. Quality of design analysis, the whole physical design flow at different target technologies (VLSI/ASIC), for GF CMOS 65 nm; Physical Synthesis and Virtual prototyping flow targeting ARM CMOS 48 nm up to TSMC FinFET 16 nm. Experience using High-Level Synthesis (HLS) from high-level abstraction modeling with SystemC, C/C++ languages and HLS tools aiming automatically-generated HDL, logic/physical synthesis for early virtual prototyping.