Area of expertise: FPGA Design & Validation
Core Technologies: Telecommunications
Experience: 17 years
Time On Site: 10%
FPGA, Digital Design and Verification: Designing Digital systems (Microprocessor based SoC, Digital Signal Processing, Packet Processing, Algorithm implementation), Verification and Test-benches (Verilog, VHDL and SystemVerilog), IO constraints, Timing closure, Static Timing Analysis (STA) and Signal Integrity (SI) with various FPGAs (Zync, Artix, Virtex, Stratix, Cyclone, ECP3).  
System-Level and High-Speed Design:  Digital system architectures ? embedded SW & HW with Toolchain, Microprocessor and DSP architectures, DDR SDRAM memory, SRAM, FLASH, MRAM, PCI, Ethernet, Mixed signal, Analog and basic RF.  
Highly experienced with Mentoring and Coaching engineers.