Experienced Digital IC Design Engineer with a proven track record and multiple successful tape-outs. Skilled in design, prototyping, and testing. Committed to working as a collaborative and positive team member, striving to utilize my knowledge and expertise in various fields around chip design to everyday challenges.
- Hardware Description Languages: SystemVerilog, Verilog, VHDL , VerilogAMS
- Programming: C, Matlab, TCL, Bash Scripting
- Synthesis / STA : Cadence Genus, Synopsys DC
- Circuit Simulation : Modelsim, Cadence Incisive, Cadence AMS, Vivaldo Design Suite, Cadence Vmanager
- Place and Route: Cadence Innovus
- Linting , CDC : Real Intent | LEC: Cadence Conformal