Experienced Senior Engineer with a demonstrated history of working in the DFT for over aa decade. Skilled 
in Synopsys and Mentor tools for Scan, ATPG and MBIST. Strong engineering professional with a Master of 
Technology (M. Tech) in VLSI Design and Embedded Systems from SJCE, Mysore. An expertise and 
dedicated team player with extensive knowledge of DFT concepts.
Skill Summary
Good understanding of MBIST implementation, verification & Post silicon support.
Worked on ATPG for stuck-at transition fault models. Full timing GLS with back annotated SDF.
Expertise in ARM shared bus MBIST implementation, debug & verification.
Fair understanding of Boundary scan and Scan
Tools used: Mentor-Tessent, Logic Vision, Fastscan, Testkompress. Synopsys- DFT Compiler, 
Tetramax, VCS & Verdi. Cadence- Encounter Test.