Digital Design and Verification Engineer

Electronic design: VHDL, Verilog, System Verilog, Virtuoso by Cadence, Spice.
Programming languages: Python object-oriented, Ansi C, Java J2SE, Haskell, Matlab, Assembler. OS: Unix/Linux, Microsoft Windows.

- Currently leading the UVM Verification activities for sensor chips for ultra-low power applications.
- Design, algorithm development and architecture development in the early stage of the projects 
- Random constrained UVM verification in System Verilog including test planning and test-bench implementation from scratch
- Verification and digital design of GPU IP-cores for wearable and portable applications
- UVM verification in System Verilog and RTL ASIC digital design in VHDL for 3D graphics core