An engineer specializing in FPGA and ASIC Design Verification.
Technical Skills
- Creating verification plans for FPGA projects;
- Developing verification components library;
- Developing layered testbenches using SystemVerilog UVM;
- Developing verification IPs (VIP);
- Developing UVM test benches (mixed SV, C) 
- Developing SystemVerilog Assertions (SVA)
- Connecting verification environments to Design Under Test (DUT)
- RTL code synthesis and implementation;