Digital Verification Engineer
- Block-level and top-level verification
- Extensive knowledge of UVM methodology
- Very familiar with Cadence flow
- Verification environment/component(UVC) development
- Formal verification
- Simulation with C test cases
- Assertion-based verification (SVA)
- Constrained random coverage driven verification (CRCDV)
- Coverage analysis and closure (code coverage and functional coverage)
- Verification plan definition (checkers, coverage, tests)
- Regression runs and debug
- Low-level and application software development (C/C++)

Programming languages: SystemVerilog, VHDL, Verilog, C, C++, Java, Perl, ITL

Protocols: OCP, APB, I2C, PMBus, AXI, UART, SPI, SVID, AHB

Tools: Cadence Xcelium, VCS, Verdi, SimVision, OneSpin