Front-end digital design and verification engineer with experience in developing IP/ASIC/FPGA using Verilog(/SystemVerilog) and VHDL. The core competencies are RTL (IP) design and verification including structural tests (linting, formal verification, CDC, test coverage etc) as well as gate level simulations. Affinity with SoC and analog modules integration aspects, interfacing to DfT and back-end teams, configuration management expertise