Highly experienced Engineering Professional in ASIC Design/Development and Electronic Design Automation (EDA). Highly experienced in ASIC / SoC Design Consulting with a major US EDA company Extensive knowledge of RTL-GDS Design Flows and methodologies, in processes down to 28nm. Now searching for a challenging role as a Principal / Senior Engineer in the ASIC / SOC industry. ? SKILLS / SPECIALITIES ? Implementation methodologies for core hardening of embedded processor IP  (Application processors / Graphics processors) ? EDA (Synthesis / DFT / Timing Analysis) to expert level ? Considerable exposure to Physical Design methodologies and flows ? Experienced in RTL development (Verilog & VHDL)  Tools Used: ? Design Compiler, DFT Compiler, Primetime ? to expert level ? ICC Compiler Power Compiler   Cadence RTL-Compiler / Encounter STA