Chipright is looking for motived senior Verification Engineers to work on the project for our client in Ireland.
Your responsibilities will be:

 	
Design and implement script-automated UVM testbench and IP creation framework.
 	
Developing architectures, methodologies and UVM testbenches for mixed signal ASIC verification.
 	
Advising on RTL and testbench architectures to maximise reuse and improve verification quality.
 	
Specifying and writing models, coverage goals and tests to reach verification targets.
 	
Scripting for and supporting use of design tools including SOS version control, DVT Eclipse and Cadence tools.
 	
Architecting, implementing and verifying on-die memory protection algorithms 
 	
Requirement tracing, verification planning and coverage analysis for signoff 

Skills Reguired:

Cadence Virtuoso
Virtuoso ADE
Modelling skills important- run simulations on analog  sims on the top level
Update models with verilogAMS
Testbench are established just need 2 guys predominantly with modelling skills to drive the design and deliver




Requirement for January

4* UVM Digital Verification Engineers

Please apply though our website or contact Natalia at natalia.bisaga@chipright.com or Adrian at adrian.holmes@chipright.com