We are looking DFT Engineer with following Skill sets.


1)      Experience implementing DFT on large SoC designs
2)      ATPG implementations using Mentor Tessent TestKompress and a fully hierarchical strategy
3)      Implementation of Scan for stuck-at and At-speed ATPG
4)      Experience with JTAG / IJTAG
5)      Silicon Bring up experience
6)      ATPG Architecture using Mentor Graphics Flow


Contact natalia.bisaga@chipright.com