Analog/RF IC Layout finFET specialist Team

Experience level: 19 years

Experience

The team Includes 3  Senior level Analog Layout engineers with many years experience working as a team remotely.

Their area of expertise fall under High Speed and RF specific blocks with experience in technologies ranging down to finFET 3nm.

Expertise

Summary:
-Implementation of Custom ESD structures

-Top Level block delivery (PLL, Low-speed Transceiver -7nm FinFET TSMC)

-Hot Plug design/layout for Thunderbolt
-IO Low-speed Transceiver (Display port Plug Detector) (16nm, 7nm FinFET)
-IO drivers operating @3.3V (16nm FINFET)
-Comparators, Amplifiers, Current mirrors, Filters, Level Shifters, Passives
-Charge Pump, Phase frequency Detector, VCO Design/Layout
-Pixel Design/Layout for X-rays imaging Mixed Signal Circuits
-Amplifiers, mixed-signal processing modules, clock recovery systems, PLLs, data converters, PWM controllers and DC-DC converters
-Layout of RF blocks, clock recovery systems, amplifiers, PLLs, data converters and DC-DC converters, High speed cells ,PLL and TX.
-RF, PLL & ADC for KU frequencies.
-Pad-ring, ESD, Rad-hard Layout
-Amplifiers, Bandgaps, Temp-sense, LFSR, Filters
-Hot Plug design/layout for Thunderbolt
-Level Shifters, Hot Plug Detector, Pixel Design/Layout
-Bi-quad Filter Design/Layout
-Modeling of circuits with Verilog-A

Technologies: 
-SOI: 28nm Samsung, 28nm ST, 22nm GF
-CMOS: 180nm Towerjazz, 150nm LFoundry  (Rad Hard), 150nm ATMEL, 140nm TSMC, 65nm ST, 45nm TSMC, 40nm, 28nm, 22nm TSMC 
-FinFET: 16nm TSMC, 7nm (coloring) TSMC, 5nm, 3nm TSMC
-SiGe: 130nm iHP
-BiCMOS: 130nm ST

Tools

Tools : 
-Virtuoso schematic editor, Virtuoso Analog Design Environment, Virtuoso Layout Suite, Spectre Circuit  Simulator, Spectre RF option, Assura Physical Verification (DRC/LVS), Quantus QRC Extraction Solution, Calibre nmDRC and nmLVS
-ADS, CST STUDIO Suite
-FINE NG of 4M, AutoCad 
-Cadence environment, Calibre, PVS, Assura, TOTEM EM-IR, PERC, MODGEN (less exposed), EOS (Calibre), Aging-SHE, EMX, Matlab

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