Verification Engineer

Salary: Very Attractive Rate
Location: N/A
Contract Lead

Verification Engineer

The Person:

  • An experienced lead verification engineer who is a confident, motivated self-starter capable of independently driving complex work packages

  • Brings 10–20 years of industry experience in ASIC/FPGA hardware development

  • A clear and articulate communicator who can collaborate effectively across cross-functional teams, time zones, and global locations

  • Shows unwavering commitment to helping the team achieve high-quality results and meet development milestones

  • Driven to learn, grow, and perform at their highest technical capability

  • Equally effective working independently or within a collaborative team environment

  • Able to quickly learn new concepts and independently acquire the skills needed for the role

Key Responsibilities:

  • Provide technical leadership, guiding projects from initial requirements through final design verification

  • Collaborate with systems and hardware engineers to define high-level testbench architectures

  • Evaluate, adopt, and integrate new Adaptive SoC toolflows and methodologies into verification environments

  • Develop, modify, and maintain random and directed tests and associated libraries in SystemVerilog/UVM

  • Write, implement, and review detailed verification test plans

  • Participate in and conduct code reviews

  • Triage, analyse, and debug regression failures

Preferred Experience:

  • Strong proficiency in advanced verification methodologies, including UVM, class-based testbenches, VIP integration, test plan creation, constrained-random testing, and coverage-driven sign-off

  • Experience with high-speed connectivity protocols (e.g., 100Gb Ethernet, PCIe Gen5/Gen6, AMBA/AXI)

  • Proficient in Python with solid understanding of build systems, regression frameworks, and CI/CD infrastructure

  • Experienced with Git-based CI/CD workflows

  • Skilled in scripting languages such as TCL, Perl, and shell

  • Familiar with verification challenges specific to Adaptive SoCs

  • Understanding of verification flows for complex embedded processor architectures (ARM, RISC-V, CPU)

  • Knowledge of software flows in advanced SoCs, including embedded processor co-simulation and debugging

  • Hands-on experience with adaptive SoC EDA tools (e.g., Vivado/Vitis)

Academic Credentials:

  • Bachelor’s or Master’s degree in Electronic Engineering, Computer Engineering, or a related discipline