Senior RTL Design Engineer – SerDes ASIC/SoC (CONTRACT Role)

📍 Location: Remote withing UK and CET time zone.

We are looking for a Senior RTL Design Engineer to develop high-performance SerDes digital logic for complex ASIC/SoC designs used in next-generation networking, AI and data center silicon.

Responsibilities:
Design and implement RTL (SystemVerilog/Verilog) for high-speed SerDes subsystems.
Develop micro-architecture, datapaths, control logic, and PCS blocks.
Integrate SerDes into large ASIC/SoC environments.
Work closely with analog, verification, and physical design teams.
Support verification, synthesis, and silicon bring-up/debug.

Requirements
10+ years of ASIC/SoC RTL design experience
Strong SystemVerilog/Verilog expertise
Experience with high-speed interfaces (PCIe, Ethernet, CXL, USB, etc.)
Solid understanding of CDC, reset architecture, and high-speed datapaths
Experience with ASIC design flows (lint, CDC, synthesis)

Nice to Have
Experience with SerDes PCS or PHY integration
Knowledge of PAM4 / high-speed IO architectures
Exposure to UVM verification or post-silicon debug

📩 If you’re passionate about building next-generation high-speed silicon, we’d love to hear from you.

Please contact me at natalia.bisaga@chipright.com