Mixed Signal Design Verification Engineer

Salary: Very Attractive Rate
Location: N/A
Contract Lead 
Mixed-Signal Design and Verification Engineer
  
Position Overview
  
We are seeking a talented and motivated Mixed-Signal Design and Verification Engineer to join our IC development team. The successful candidate will be responsible for the design, modeling, and verification of analog and mixed-signal IPs integrated into complex SoCs. This role involves hands-on transistor-level design as well as behavioral modeling and mixed-signal verification using state-of-the-art EDA tools and methodologies.
  
Key Responsibilities
  
Design
  
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    Design and simulate analog and mixed-signal circuits such as ADCs, DACs, PLLs, bandgaps, amplifiers, LDOs, and sensor interfaces.
     	
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    Perform schematic entry, transistor-level simulation, and layout supervision using Cadence Virtuoso or equivalent design environments.
     	
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    Develop behavioral models (Verilog-A, Verilog-AMS, or real-number models) for system-level simulations and verification.
     	
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    Conduct PVT and Monte Carlo analysis to ensure circuit robustness and yield.
     	
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    Collaborate with layout engineers to optimize performance, area, and reliability.
     	
  
Verification
  
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    Develop and execute mixed-signal verification environments integrating analog and digital domains.
     	
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    Create SystemVerilog/UVM or Verilog-AMS testbenches for block-level and top-level verification.
     	
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    Perform co-simulation using AMS tools (e.g., Cadence AMS Designer, Synopsys VCS AMS, or Mentor Questa ADMS).
     	
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    Develop and maintain real-number models (RNMs) to accelerate full-chip verification.
     	
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    Define verification plans, coverage metrics, and automated regression flows.
     	
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    Debug simulation results and correlate design behavior across schematic, behavioral, and silicon domains.
     	
  
Collaboration
  
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    Work closely with system architects, digital design, and validation teams to define specifications and interface requirements.
     	
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    Support post-silicon validation, measurement correlation, and root-cause analysis of issues.
     	
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    Document design methodologies, results, and best practices for reuse across projects.
     	
  
Required Qualifications
  
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    Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field.
     	
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    3+ years of experience in analog/mixed-signal circuit design and verification.
     	
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    Strong proficiency in Cadence Virtuoso, Spectre, or similar SPICE-based tools.
     	
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    Experience with SystemVerilog/UVM, Verilog-AMS, or real-number modeling.
     	
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    Solid understanding of analog and digital fundamentals, including sampling theory, noise, linearity, and timing analysis.
     	
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    Proficiency in scripting (Python, Perl, TCL) for simulation automation and data processing.