- DFT insertion using Cadence (Genus/Innovus)
- OCC insertion for at-speed transition fault test
- ATPG with Cadence Modus
- Coverage diagnosis back to RTL/architecture
- Stitching of both soft and hard third-party IP with embedded scan chains into our design.
- Pattern verification with back-annotated gate-simulation using Cadence Xcelium
- Power analysis of patterns.
- Memory BIST insertion with Cadence Modus.
The candidate will work closely with our implementation engineer to set up the tool-chain for DFT-insertion (synthesis, PnR). They will be expected to analyse the resulting netlists to ensure our design and implementation flow outputs high test-coverage results. Feedback should be provided to optimise the flow and the RTL design to meet targets compatible with an automotive device. ATPG patterns must be generated, verified with back-annotated gate-simulations and handed off to our test engineer.