{"ID":19046,"post_author":"132","post_date":"2024-09-20 09:43:04","post_date_gmt":"2024-09-20 08:43:04","post_content":"Top and block level digital implementation and signoff activities. Planning and managing physical design \ntasks for a successful chip implementation. Requirements gathering and customer interaction. Flow \ndevelopment in Cadence EDA (Innovus, QRC, Tempus, Voltus, Conformal) and Calibre DRC\/ERC\/LVS\/ANT. \nRnD team guidance for timing constraints and synthesis activities.","post_title":"E-8196","post_excerpt":"","post_status":"publish","comment_status":"open","ping_status":"open","post_password":"","post_name":"e-8196","to_ping":"","pinged":"","post_modified":"2024-09-20 09:43:04","post_modified_gmt":"2024-09-20 08:43:04","post_content_filtered":"","post_parent":0,"guid":"http:\/\/www.chipright.com\/candidate\/e-8196\/","menu_order":0,"post_type":"candidate","post_mime_type":"","comment_count":"0","filter":"raw","meta":{"_edit_lock":"1737112773:132","level":"Senior Level Expert (Principle Engineer)","contact":"Natalia Bisaga","experience":"12","entity_type":"Individual","on_site":"10","technologies":"Artificial Intelligence (AI)","best_fit":"ASIC Digital Layout & Physical Design","desired_position":"Contract"}}

NO

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E-8196 | Chipright Chipright

E-8196

Area of expertise: ASIC Digital Layout & Physical Design

Core Technologies: Artificial Intelligence (AI)

Experience: 12 years

Time On Site: 10%

Top and block level digital implementation and signoff activities. Planning and managing physical design 
tasks for a successful chip implementation. Requirements gathering and customer interaction. Flow 
development in Cadence EDA (Innovus, QRC, Tempus, Voltus, Conformal) and Calibre DRC/ERC/LVS/ANT. 
RnD team guidance for timing constraints and synthesis activities.

Contact Us

+353 91 444 168

info@chipright.com

Unit 8B, Galway Technology Centre, Galway, Ireland

E-8196

Area of expertise: ASIC Digital Layout & Physical Design

Core Technologies: Artificial Intelligence (AI)

Experience: 12 years

Time On Site: 10%

Top and block level digital implementation and signoff activities. Planning and managing physical design 
tasks for a successful chip implementation. Requirements gathering and customer interaction. Flow 
development in Cadence EDA (Innovus, QRC, Tempus, Voltus, Conformal) and Calibre DRC/ERC/LVS/ANT. 
RnD team guidance for timing constraints and synthesis activities.

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