ASIC Verification Engineer with years of strong experience in SystemVerilog/UVM-based verification of complex SoC and subsystem designs.
 	
Proven track record in developing verification environments, VIPs, scoreboards, and coverage-driven verification strategies across Ethernet, LPDDR4, CAN, and memory interface subsystems.
 	
Experienced in achieving full functional and code coverage, debugging complex RTL issues, and integrating AXI/AHB-based architectures.
 	
Skilled in using industry-standard tools including VCS, Questa, and NCSIM.
 	
Hands-on experience with RISC-V SoC verification and automation using Python and Rust. Demonstrated leadership in coordinating engineering teams, mentoring junior engineers, and supporting hiring processes.
 	
Strong academic background in embedded systems and digital design.