Digital Design & Verification Engineer
 	
Digital hardware design, functional verification, FPGA/ASIC development, HPC architectures
 	
Languages: Verilog, SystemVerilog, VHDL, SystemC
 	
Methodologies: UVM, constrained-random verification, functional coverage, SystemVerilog Assertions (SVA)
 	
Top-level verification of Arm-based HPC processors (AMBA: CHI, AXI, APB, ATB, Low Power Interface)
 	
Design & integration of IEEE 754 / RISC-V compliant Vector Floating-Point Unit (FPU)
 	
H.265/HEVC accelerator design optimized for FPGA
 	
Coverage automation with Tcl scripting
 	
Programming & Scripting: C, C++, MATLAB; Tcl, Bash, Python
 	
Simulation & Verification: Siemens QuestaSim, Cadence Xcelium, Synopsys VCS, Polarion ALM, Questa Verification Run Manager
 	
Synthesis & Design: AMD Vivado, Cadence Genus
 	
PCB Design: Altium Designer
 	
Version Control: Git