Full Custom top level layout experience from 0.18um to 7nm including advanced Fin-FET technologies in various PDKs.
 	
-Experience both in active and passive designs
 	
-Passing entire verification process (LVS, DRC, ESD, Antenna, ERC, DFM)
 	
-Knowledge of layout techniques (matching, latch-up prevention, shielding, reducing parasitic capacitance and electro-migration effects)
 	
-Optimized floor-planning and power routing
 	
-Cadence SKILL programming. Writing scripts for repeatable tasks (creating specific type of routing, placing array of pins or labels, generating specific structures)
 	
-Cadence (Virtuoso, Virtuoso XL), Synopsys (ICV), Mentor Graphics (Calibre) platforms