{"ID":21769,"post_author":"129","post_date":"2025-10-24 09:34:46","post_date_gmt":"2025-10-24 08:34:46","post_content":"

Digital Verification Engineering with experience across unit-level, slice-level, and mixed-signal verification<\/li>\r\n \t
Verification methodologies: UVM, OVM (Universal\/ Open Verification Methodology)<\/li>\r\n \t
Simulation Tools: Cadence IUS, Mentor Graphics QuestaSim<\/li>\r\n \t
Performance\/Debugging Tools: Custom-built environments for latency, throughput, and transaction monitoring<\/li>\r\n \t
Modeling & Design Tools: MATLAB, Simulink, LabVIEW<\/li>\r\n \t
Functional and constraint-based verification, coverage analysis, and regression testing<\/li>\r\n \t
Strong debugging, performance checking, and test environment development capabilities<\/li>\r\n \t
Configuration & Revision Control: Git, SVN, Perforce, ClearCase<\/li>\r\n \t
Protocols & Interfaces: SPI, AMBA<\/li>\r\n<\/ul>","post_title":"E-67141","post_excerpt":"","post_status":"publish","comment_status":"open","ping_status":"open","post_password":"","post_name":"e-67141","to_ping":"","pinged":"","post_modified":"2025-10-24 09:35:31","post_modified_gmt":"2025-10-24 08:35:31","post_content_filtered":"","post_parent":0,"guid":"http:\/\/www.chipright.com\/candidate\/e-67141\/","menu_order":0,"post_type":"candidate","post_mime_type":"","comment_count":"0","filter":"raw","meta":{"desired_position":"Contract","best_fit":"ASIC Verification","experience":"8","entity_type":"Individual","on_site":"10","technologies":"Telecommunications","contact":"Alison Freer","level":"Senior Engineer","_edit_lock":"1761294931:129","_edit_last":"129"}}

NO

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E-67141 | Chipright Chipright

E-67141

Area of expertise: ASIC Verification

Core Technologies: Telecommunications

Experience: 8 years

Time On Site: 10%


 	Digital Verification Engineering with experience across unit-level, slice-level, and mixed-signal verification
 	Verification methodologies: UVM, OVM (Universal/ Open Verification Methodology)
 	Simulation Tools: Cadence IUS, Mentor Graphics QuestaSim
 	Performance/Debugging Tools: Custom-built environments for latency, throughput, and transaction monitoring
 	Modeling & Design Tools: MATLAB, Simulink, LabVIEW
 	Functional and constraint-based verification, coverage analysis, and regression testing
 	Strong debugging, performance checking, and test environment development capabilities
 	Configuration & Revision Control: Git, SVN, Perforce, ClearCase
 	Protocols & Interfaces: SPI, AMBA

Contact Us

+353 91 444 168

info@chipright.com

Unit 8B, Galway Technology Centre, Galway, Ireland

E-67141

Area of expertise: ASIC Verification

Core Technologies: Telecommunications

Experience: 8 years

Time On Site: 10%


 	Digital Verification Engineering with experience across unit-level, slice-level, and mixed-signal verification
 	Verification methodologies: UVM, OVM (Universal/ Open Verification Methodology)
 	Simulation Tools: Cadence IUS, Mentor Graphics QuestaSim
 	Performance/Debugging Tools: Custom-built environments for latency, throughput, and transaction monitoring
 	Modeling & Design Tools: MATLAB, Simulink, LabVIEW
 	Functional and constraint-based verification, coverage analysis, and regression testing
 	Strong debugging, performance checking, and test environment development capabilities
 	Configuration & Revision Control: Git, SVN, Perforce, ClearCase
 	Protocols & Interfaces: SPI, AMBA

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E-67141

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