Complete physical implementation of complex digital SoCs, from gate level to gdsII, focusing on all aspects of design closure: Floorplan, Power routing, Place&Route, Clock tree implementation and CCD optimization, redundant via insertion and chip finishing, metal fill creation, RC extraction, DRCs & schematic-to-layout verification, antenna fixing, STA and closure, SI, LEC. Top-level and block-level design experience.
 	
Hierarchical design flow with Synopsys ICC tool.
 	
Flow development for designs at very low technology nodes with ICC and ICC2. NDM lib preparation flow.
 	
Timing constraints experience.
 	
TCl scripting.
 	
Experience with various technology nodes down to very low sub-micron processes