Mixed Signal Verification Engineer in the mixed-signal domain from block up to top-level system (even multichip, multi PDK):
 	
-Expertise with large command-line based environments for both DoT and AoT in multi-chip products
 	
-Great debug of XRUN with various configurations (Sch+Models+RTL, Full-RNM, Sch+GL)
 	
-Setting up verification environments both within Virtuoso and command-line environments
 	
-UVM environment expertise in mixed-signal context (test, checkers, configs, seq)
 	
-Power user of Virtuoso with schematic and layout experience
 	
-Expert level modeling ability in most industry relevant modelling languages and abstractions
 	
-Verilog-A/AMS or SPICE for speed improvement of complex designs
 	
-RNM (Verilog/ System-Verilog) discreet modeling for top level fully digital verification
 	
-Experience with rare languages (MAST, VHDL-AMS, PSPICE)
 	
-MATLAB mathematical modeling for design purposes
 	
-Hands on "in silicon" design of analog sub-systems