Area of expertise: ASIC Digital Layout & Physical Design
Core Technologies: Telecommunications
Experience: 15 years
Time On Site: 50%
Exceptional technical experience in semiconductor design and IC design using knowledge of physical design methods for digital & analog circuits. Expertise in RTL2GDS including RTL Integration , RTL Analysis , Synthesis , Static Timing Analysis , Formal Verification , Place and Route for ASIC physical implementation, timing closure, signal integrity, low power implementation, (LVS/DRC and LEC/CLP. Extensive experience of Floor Planning, CTS, timing to meeting design requirements for area, power & timing. Tapeout experience with 10nm, 14nm, 16nm, 40m, 65nm, 90nm, 130nm and 180nm designs