Senior Analog Layout & Design Engineer.
Layout and verification of mixed-signal and RF IP blocks (LNAs, bandgaps, regulators, ADCs, DACs, LDOs, Buck converters, etc) using 180nm, 150nm, 65nm, 40nm, 28nm, 20nm, 16nm, 14nm, 7nm process nodes (TSMC, Global Foundries, Samsung, TowerJazz)
Cadence Virtuoso XL ICADV, ADEXL, Assura, Spectre, EAD, Voltus, Pegasus, design, layout and verification tools
Synopsys Custom Compiler, Galaxy P&R, Hercules, HSpice, design, layout and verification tools Mentor Calibre LVS, DRC, RCX verification tools
Transistor level design in various CMOS nodes
Silicon debug, evaluation, test and characterization.