Sr AMS Verification Engineer
-Analog and Mixed-signal IP and Top-Level Verification, modeling of
analog circuits and model validation
-Cadence tools, SystemVerilog (UVM), Verilog-AMS,
SystemVerilog, Python, etc.
-Battery management system ? top-level mixed-signal verification and modeling
-Analog IP modeling: Highly optimized PMIC with high efficiency converters;
Virtuoso, ADE-Explorer, ADE-Maestro