Area of expertise: FPGA Design & Validation
Core Technologies: Aerospace
Experience: 20 years
Time On Site: 20%
ASIC and FPGA code development in Verilog and VHDL Technical Programming languages C / Assembly SystemVerilog / Verilog / VHDL Operating System Windows Linux Tools Cadence Paladium, Cadence Xtreme III, Cadence AXIS, Synopsys Design Compiler, Synplicity Certify and Synplify Pro, Xilinx ISE, Xilinx EDK, Vivado Altera Quartus Cadence NCSim, Mentor Graphics Modelsim Matlab, Visual C Development equipment Various development Micronas and Bosch ProDesign CHIPit gold and platinum edition. Custom created boards with Spartan6, Artix, Virtex 7 (and older) and Xilinx CPLDs Standards and protocols AXI4, SDRAM / DDR3 SDRAM, various bus protocols (I2C, SPI, SSP), IEEE 802.3 (Ethernet), IEEE 1149.1 (JTAG), USB DO-254 ISO 26262