E-79115

Area of expertise: Analog Layout
Core Technologies: Consumer Electronics
Experience: 8 years
Time On Site: 10% 
    
 	
  • -Experienced Analog Layout Engineer
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  • -Current experience- working on FinFet technologies including TSMC 3nm, 4nm, 7nm, nanosheet technology 2n
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  • -Floorplan and estimation on cell and Megacell level
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  • -Verification tools e.g. DRC,LVS,ERC, Voltus
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  • -Virtuoso 23.1 Cadence tools like WSP, Place and Route, Concurrent Layout Editor, main layout tasks on Serdes, CLK, PLL,
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  • -Layout reviews internally and with the customer
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  • -Preparing documentation and presentations for the customer
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