{"ID":20962,"post_author":"129","post_date":"2025-07-16 09:48:35","post_date_gmt":"2025-07-16 08:48:35","post_content":"

-Experienced Analog Layout Engineer<\/li>\r\n \t
-Current experience- working on FinFet technologies including TSMC 3nm, 4nm, 7nm, nanosheet technology 2n<\/li>\r\n \t
-Floorplan and estimation on cell and Megacell level<\/li>\r\n \t
-Verification tools e.g. DRC,LVS,ERC, Voltus<\/li>\r\n \t
-Virtuoso 23.1 Cadence tools like WSP, Place and Route, Concurrent Layout Editor, main layout tasks on Serdes, CLK, PLL,<\/li>\r\n \t
-Layout reviews internally and with the customer<\/li>\r\n \t
-Preparing documentation and presentations for the customer<\/li>\r\n<\/ul>","post_title":"E-79115","post_excerpt":"","post_status":"publish","comment_status":"open","ping_status":"open","post_password":"","post_name":"e-79115","to_ping":"","pinged":"","post_modified":"2025-07-16 10:09:48","post_modified_gmt":"2025-07-16 09:09:48","post_content_filtered":"","post_parent":0,"guid":"http:\/\/www.chipright.com\/candidate\/e-79115\/","menu_order":0,"post_type":"candidate","post_mime_type":"","comment_count":"0","filter":"raw","meta":{"desired_position":"Contract","best_fit":"Analog Layout","experience":"8","entity_type":"Individual","on_site":"10","technologies":"Consumer Electronics","contact":"Amy Hardiman","level":"Senior Engineer","_edit_lock":"1752664012:132","_edit_last":"129"}}

NO

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E-79115 | Chipright Chipright

E-79115

Area of expertise: Analog Layout

Core Technologies: Consumer Electronics

Experience: 8 years

Time On Site: 10%


 	-Experienced Analog Layout Engineer
 	-Current experience- working on FinFet technologies including TSMC 3nm, 4nm, 7nm, nanosheet technology 2n
 	-Floorplan and estimation on cell and Megacell level
 	-Verification tools e.g. DRC,LVS,ERC, Voltus
 	-Virtuoso 23.1 Cadence tools like WSP, Place and Route, Concurrent Layout Editor, main layout tasks on Serdes, CLK, PLL,
 	-Layout reviews internally and with the customer
 	-Preparing documentation and presentations for the customer

Contact Us

+353 91 444 168

info@chipright.com

Unit 8B, Galway Technology Centre, Galway, Ireland

E-79115

Area of expertise: Analog Layout

Core Technologies: Consumer Electronics

Experience: 8 years

Time On Site: 10%


 	-Experienced Analog Layout Engineer
 	-Current experience- working on FinFet technologies including TSMC 3nm, 4nm, 7nm, nanosheet technology 2n
 	-Floorplan and estimation on cell and Megacell level
 	-Verification tools e.g. DRC,LVS,ERC, Voltus
 	-Virtuoso 23.1 Cadence tools like WSP, Place and Route, Concurrent Layout Editor, main layout tasks on Serdes, CLK, PLL,
 	-Layout reviews internally and with the customer
 	-Preparing documentation and presentations for the customer

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