{"ID":18977,"post_author":"132","post_date":"2025-09-25 09:43:01","post_date_gmt":"2025-09-25 08:43:01","post_content":"

Verification language: SystemVerilog (UVM) - several years' experience Python, C, C++<\/li>\r\n \t
Simulators: Cadence Xcelium\/IES\/NCSim, Synopsys VCS, Mentor ModelSim<\/li>\r\n \t
Protocols: AXI, DisplayPort, MIPI SCI2<\/li>\r\n \t
Projects:<\/li>\r\n \t
- Verification of MIPI CSI2 Transmitter<\/li>\r\n \t
- DisplayPort VIP (DisplayPort version 1.3)<\/li>\r\n \t
- DDR Cache Controller<\/li>\r\n \t
- W2N (wide-to-narrow) adapter<\/li>\r\n \t
- NVMe Inbound Controller<\/li>\r\n \t
- IP for Hardware Acceleration of Write Commands<\/li>\r\n \t
- IP for Buffer Management between System side (internal protocol) and Host side (NVMe)<\/li>\r\n<\/ul>","post_title":"E-76382","post_excerpt":"","post_status":"publish","comment_status":"open","ping_status":"open","post_password":"","post_name":"e-76382","to_ping":"","pinged":"","post_modified":"2025-09-25 09:57:44","post_modified_gmt":"2025-09-25 08:57:44","post_content_filtered":"","post_parent":0,"guid":"http:\/\/www.chipright.com\/candidate\/e-76382\/","menu_order":0,"post_type":"candidate","post_mime_type":"","comment_count":"0","filter":"raw","meta":{"desired_position":"Contract","best_fit":"ASIC Verification","experience":"8","entity_type":"Individual","on_site":"0","technologies":"5G","contact":"Alison Freer","level":"Senior Level Expert (Principle Engineer)","_edit_lock":"1758791104:129","_edit_last":"129"}}

NO

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E-76382 | Chipright Chipright

E-76382

Area of expertise: ASIC Verification

Core Technologies: 5G

Experience: 8 years

Time On Site: 0%


 	Verification language: SystemVerilog (UVM) - several years' experience Python, C, C++
 	Simulators: Cadence Xcelium/IES/NCSim, Synopsys VCS, Mentor ModelSim
 	Protocols: AXI, DisplayPort, MIPI SCI2
 	Projects:
 	- Verification of MIPI CSI2 Transmitter
 	- DisplayPort VIP (DisplayPort version 1.3)
 	- DDR Cache Controller
 	- W2N (wide-to-narrow) adapter
 	- NVMe Inbound Controller
 	- IP for Hardware Acceleration of Write Commands
 	- IP for Buffer Management between System side (internal protocol) and Host side (NVMe)

Contact Us

+353 91 444 168

info@chipright.com

Unit 8B, Galway Technology Centre, Galway, Ireland

E-76382

Area of expertise: ASIC Verification

Core Technologies: 5G

Experience: 8 years

Time On Site: 0%


 	Verification language: SystemVerilog (UVM) - several years' experience Python, C, C++
 	Simulators: Cadence Xcelium/IES/NCSim, Synopsys VCS, Mentor ModelSim
 	Protocols: AXI, DisplayPort, MIPI SCI2
 	Projects:
 	- Verification of MIPI CSI2 Transmitter
 	- DisplayPort VIP (DisplayPort version 1.3)
 	- DDR Cache Controller
 	- W2N (wide-to-narrow) adapter
 	- NVMe Inbound Controller
 	- IP for Hardware Acceleration of Write Commands
 	- IP for Buffer Management between System side (internal protocol) and Host side (NVMe)

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