Verification Engineer with experience in ASIC/FPGA design verification, specializing in SystemVerilog/UVM-based verification environments for IP and subsystem-level designs.
 	
Experienced in developing verification plans, custom UVCs, RAL tests, scoreboards, and functional coverage models, with strong focus on achieving full coverage closure.
 	
Hands-on experience verifying communication and control IPs including Watchdog, Register Latch, LIN, K-Line, and Radar subsystems, using protocols such as APB, SPI, I2C, and UART.
 	
Skilled in both simulation-based verification and formal verification using JasperGold, including SVA development and formal coverage analysis.
 	
Experienced with Cadence verification tools including Xcelium and vManager, and working within structured verification flows.
 	
Demonstrates strong collaboration with RTL designers and client teams, including presenting verification strategies and project results.
 	
Exposure to top-level integration testing.