Digital Verification Engineer with experience in ASIC/SoC verification, specializing in SystemVerilog and UVM-based verification environments.
 	
Strong background in SoC and module-level verification, working across complex digital, mixed-signal, and safety-critical designs including Baseband SoCs, BLE devices, MCU subsystems, and memory controllers.
 	
Experienced in developing self-checking UVM testbenches, verification plans, scoreboards, and constrained-random regressions, with hands-on use of Cadence Xcelium and vManager flows.
 	
Proven experience verifying protocols including AXI, AHB, APB, SPI, BLE, JTAG, and DDR3. Worked within ISO 26262 and IEC safety-compliant projects, contributing to automotive and safety-critical systems.
 	
Strong collaboration skills with experience mentoring engineers and supporting regression infrastructure.
 	
Additional background in embedded firmware development for ARM microcontrollers and IoT systems.