-Verification engineer with fast learning skills and a high capability for solving problems
 	
 -Developing and executing comprehensive verification plans using SystemVerilog and UVM methodologies
 	
 -Authoring detailed documentation covering the verification strategy and environment architecture
 	
 -The entire verification flow: from understanding module specifications to closing meeting
 	
 -RTL debug and run regressions
 	
 -Debugging and reporting issues in coordination with design and integration teams
 	
 -Analyzing and improving code and functional coverage metrics
 	
 -Maintaining and enhancing existing verification environments
 	
 -Taking over and advancing incomplete verification projects
 	
 -Python model integration in the verification environment
 	
 -Directed and Random Testing
 	
 -Creating and integrating custom UVCs for internal