Mixed Signal Verification Engineer:
 	
Experience in:
 	
Writing UVM tests in SystemVerilog
 	
Edit of the UVM base classes
 	
Behavioral models in SystemVerilog and Verilog-AMS
 	
Digital, Analog and Mixed-signal simulations in Cadence
 	
Design support (design, modelling, verification) engineer for various automotive projects
 	
Mixed-Signal Verification of PMIC products
 	
Verification for different blocks (LDOs, Buck and Boost converters, Bandgap, voltage monitoring blocks
 	
Experience in projects: Power switches, Linear regulators, Power converters.