Senior Digital Verification Engineer with years of hands-on experience in IP, subsystem, and top-level verification across automotive, aerospace, consumer electronics, and industrial domains.
 	
Deep expertise in SystemVerilog/UVM and Specman/E, with a strong track record of building constrained-random, coverage- driven testbenches from scratch for complex SoC IPs.
 	
Proven capability in functional safety (DO-254, SIL4) verification flows, cross-vendor EDA tool usage, and collaboration with Tier-1 semiconductor companies including Infineon, Bosch, Intel, Socionext, Thales, and Alcatel-Lucent