Analog IC Layout Engineer
Salary: Attractive Rate
Location:
Contract
Senior Analog IC Layout Engineer
- Experienced analog IC layout,
- Coarse geometry, 0.35um CMOS
- Experience in Cadence tools , ASSURA DRC LVS , PVS DRC LVS, and QRC
- Experience in Mentor Calibre Tools DRC LVS and Parasitic Extraction
Contact Us
+353 91 444 168
info@chipright.com
Unit 8B, Galway Technology Centre, Galway, Ireland