Senior Digital ASIC Verification Engineer with years of SystemVerilog/UVM experience specializing in Metric
 	
Driven Verification. Owned full verification lifecycle for 10M+ gate IP cores within a 100M+ gate subsystem,
 	
Driving designs from test plan through 100% coverage closure across 3 tapeouts.
 	
Deployed UVM testbenches from scratch, utilized MATLAB reference models for bit-exact checking, and applied SVA/Formal Verification for control logic.
 	
Experience with AXI/AHB/APB protocols.